MIPI Debug Target IP

MIPI Debug Target interface IP provides full support for the two-wire MIPI Debug Target synchronous serial interface, compatible with MIPI Debug Specification version 1.0. Through its MIPI Debug Target compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI Debug Target IP is proven in FPGA environment. The host interface of the MIPI Debug Target can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

• see the entire MIPI Debug Target IP datasheet
• get in contact with MIPI Debug Target IP Supplier