MIPI DPHY1.2 RX (support combo TTL, LVDS, HiSPI)

The Innosilicon MIPI D-PHY IP provides D-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, plus a MIPI® low-power low speed receiver that supports data transfer in the bi-directional mode.
The D-PHY is built in with a standard PPI digital interface to talk to any third-party Host controller.
This enables a seamless implementation allowing interface to D-PHY based sensors. The Innosilicon I/O and ESD are also built-in as one in a rectangular footprint. It is optimized for High-speed applications with robust timing and small silicon area.
The D-PHY supports the electrical portion of MIPI D-PHY V1.2 Standard, covering all transmission modes (ULP/LP/HS). This IP cost-effectively adds MIPI D-PHY capability to any SOC used in communication and consumer electronics field.

• see the entire MIPI DPHY1.2 RX (support combo TTL, LVDS, HiSPI) datasheet
• get in contact with MIPI DPHY1.2 RX (support combo TTL, LVDS, HiSPI) Supplier