TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries, multiple metalstacks
MIPI DSI-2 TX Controller
The IP supports both command and video modes, ensuring efficient operation across diverse display use cases. It fully implements all three layers defined by the DSI-2 standard: Pixel-to-Byte Packing, Low-Level Protocol, and Lane Management. With a 64-bit core width, the DSI-2 Controller distributes data across 4 lanes via a 16-bit PPI.
Programmable via the APB bus, the DSI-2 Controller includes interrupt ports for status and error monitoring. It has been rigorously function-verified through VIP, ensuring robust performance.
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Block Diagram of the MIPI DSI-2 TX Controller IP Core
![MIPI DSI-2 TX Controller Block Diagam](http://www.design-reuse.com/sip/blockdiagram/54872/20240718042128-main-DSI-2-TX.png)