MIPI I3C MASTER

Features

• Compliant with the MIPI Alliance Draft Specification for I3C v1.x
• I3C Master Features
• Supports all modes of Master – SDR, HDR and HDR-DDR,I2C Modes
• Can be configured to work as secondary master also.
• Dynamic addressing assignment capability
• Support for slave generated inband interrupts.
• Memory for retaining bus device addresses.
• I3C Slave Features
• Supports I3C slave configuration – HDR-DDR Slave, SDR Only Slave.
• Common Slave IP can be instantiated many times to have multiple slaves on the I3C bus.
• Dynamic address complaint.
• Supports/Tolerate I3C global command codes.
• Master Interface for system access : APB. Optionally AXI.
• Slave Interface for Register access : APB
• Configurable FIFOs

Block Diagram of the MIPI I3C MASTER IP Core