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MIPI RFFE Master IP Core
The MIPI RFFE Master controller IP is a highly optimized and technology agnostic implementation of the MIPI RFFE v.3.1 standard targeting both ASIC and FPGA technologies. This IP is used to connect a digital RFIC to RF front end components, like Power Amplifiers (PA), Low-Noise Amplifiers (LNA), filters, switches, power management modules, Antenna Turner and Sensors, which are considered RFFE Slaves.
It supports up to 15 slaves and 4 masters that can be connected through RFFE bus. This MIPI RFFE Master IP is backward compatible with MIPI RFFE components version 3.0, 2.1, 2.0 and 1.0.
The IP-core has been heavily tested in System Verilog random regression environment.
It supports up to 15 slaves and 4 masters that can be connected through RFFE bus. This MIPI RFFE Master IP is backward compatible with MIPI RFFE components version 3.0, 2.1, 2.0 and 1.0.
The IP-core has been heavily tested in System Verilog random regression environment.
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Block Diagram of the MIPI RFFE Master IP Core IP Core
