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Multi Channel FIR Filter
Finite Impulse Response (FIR) filters are important building blocks in signal processing.
beam processing, diffraction compensation, equalisation and various signal processing applications. Many applications often involve filtering multiple data channels simultaneously, raising concerns about resource utilization. This design implements a multi-channel FIR filter (MFF) which allows multiple FIR filters to use the same hardware in a sequential manner, optimizing resource utilization. This MFF is a viable solution particularly suited for scenarios characterized by low data rates relative to the system clock.
In this design, data and coefficient widths, number of data channels and filter taps are all user selectable. All FIR filters have an identical number of taps. Filter taps can have the same or different values. MFF output width, as well as internal multiplier output width are also user selectable. This allows the user to optimize the filter outputs and resource utilization.
The MFF is implemented using VHDL and capable of being used on any FPGA/ASIC architecture.
beam processing, diffraction compensation, equalisation and various signal processing applications. Many applications often involve filtering multiple data channels simultaneously, raising concerns about resource utilization. This design implements a multi-channel FIR filter (MFF) which allows multiple FIR filters to use the same hardware in a sequential manner, optimizing resource utilization. This MFF is a viable solution particularly suited for scenarios characterized by low data rates relative to the system clock.
In this design, data and coefficient widths, number of data channels and filter taps are all user selectable. All FIR filters have an identical number of taps. Filter taps can have the same or different values. MFF output width, as well as internal multiplier output width are also user selectable. This allows the user to optimize the filter outputs and resource utilization.
The MFF is implemented using VHDL and capable of being used on any FPGA/ASIC architecture.
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Block Diagram of the Multi Channel FIR Filter IP Core
