Multi-Protocol Physical Medium Attachment Sublayer

Features

• Low-Jitter PLL
• 10MHz-to-700MHz Wide-Range Reference Clock Frequency
• Spread Spectrum Clocking (SSC)
• High-Precision Bias (BGR)
• Termination Resistance Calibration
• PLL Lock Range Calibration
• TX Lane-to-Lane Output Timing De-Skew
• Frequency-Divided PLL Clock Output
• 27MHz RC-Oscillator
• Duty Cycle Correction
• Analog Monitor Output
• Full-duplex transceivers at serial data rete between 0.6Gbps to 12.5Gbps
• Utilize Global Foundries 40nm technology
• Requires supply voltage level of 1.1V, and 1.8V or 2.5V on second PMA voltage supply
• Supports spread spectrum clocking (SSC) for EMI reduction
• Calibrated on-chip termination
• Three-tap TX equalizer (de-emphasis)
• Adaptive continuous time linear equalizer (CTLE) and decision feedback equalization (DFE)
• Squelch circuit with programmable threshold for support of OOB in SAS and SATA and TX idle for PCIe
• IEEE 1149.1(DC) and 1149.6 (AC) JTAG boundary scan support