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Multiplier
The multiplier operation is essential and abundant in DSP Applications. Achieving maximum implementation efficiency and clock performance is therefore critical to DSP systems and frequently presents a significant challenge to hardware engineers.
The Multiplier LogiCORE™ simplifies this challenge by abstracting away FPGA device specifics, while maintaining the required maximum performance and resource efficiency. The multiplier is able to generate parallel multipliers, and constant coefficient multipliers, both with differing implementation styles. Furthermore, with the aid of instantaneous resource estimation, hardware engineers can rapidly select the optimal solution for their system.
This IP provides fine control over the latency (pipelining) of the multipliers (purely combinatorial to fully pipelined) and symmetric rounding implemented in the DSP48 slice. Fully pipelined implementations enable maximum clock frequency performance
The Multiplier LogiCORE™ simplifies this challenge by abstracting away FPGA device specifics, while maintaining the required maximum performance and resource efficiency. The multiplier is able to generate parallel multipliers, and constant coefficient multipliers, both with differing implementation styles. Furthermore, with the aid of instantaneous resource estimation, hardware engineers can rapidly select the optimal solution for their system.
This IP provides fine control over the latency (pipelining) of the multipliers (purely combinatorial to fully pipelined) and symmetric rounding implemented in the DSP48 slice. Fully pipelined implementations enable maximum clock frequency performance
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