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400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
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Multiprocessor, 4-Way Simultaneous Multithreading
Features
- Efficient Throughput
- Efficient data-centric processing with simultaneous multi-threading (SMT), low latency and deterministic data access
- 3-Wide, 9-stage, in-order pipeline with 1-, 2-, 4-way SMT
- RISC-V Compliant ISA
- RV64GHZ + Bitmanip Zba and Zbb, + CMO Extension
- MIPS User-Defined Instructions (UDI)—Cache and TLB management, Performance enhancements and DVM (Distributed Virtual Memory) support
- Optional 64KB Data ScratchPad RAM (DSPRAM) for real-time, low-latency applications
- Coherence Manager
- Support for up to 8 coherent initiators comprising of either MIPS RISC-V Processors or 3rd party accelerators
- Cluster Level-2 Cache L2$ up to 8MB
- HW pre-fetch, widened busses, reduced latency
- System interface:
- ACE or AXI: 256-bit system bus
- Optional: Non-coherent periphery bus (up to 4 ports)
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Block Diagram of the Multiprocessor, 4-Way Simultaneous Multithreading IP Core
RISC-V IP
- RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications
- ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
- 32-bit Embedded RISC-V Functional Safety Processor
- 64-bit RISC-V Application Processor Core
- Dual-issue Linux-capable RISC-V core