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NVMe Host Accelerator
The IntelliProp IPC-NV164A-HI NVMe Host Accelerator IP Core provides a simplified, high-bandwidth interface to industry standard NVMe storage devices.
The IntelliProp NVMe Host Accelerator IP Core provides a small footprint processor register interface or RTL state-machine register interface for data movement between a user-defined data buffer and an NVMe target. Additionally, the NVMe Host Accelerator IP Core requires minimal knowledge of the PCIe and NVMe specification. The IP Core handles initialization of the PCIe Root Complex, building command submissions, parsing command
completions.
The protocol interface is compliant to the NVMe 1.4 specification and is fully verified using a coverage driven methodology in pseudo random simulation.
The IPC-NV164A-HI NVMe Host Accelerator IP Core provides a simple firmware or RTL driven interface for data movement to and from an NVMe endpoint attached to a PCIe link. The interface to the IP core is designed to be driven by a User Logic state machine or processor. All command submission and completion queues are managed by the internal state machines. Users will write command submission context to the Command Registers or direct wire connections and arm the Command Submission State Machine to issue a command to the NVMe endpoint. Users will read command completion context from the Command Registers or direct wire connections when command completions have been parsed by the Command Completion State Machine.
The NVMe Host Accelerator IP Core can be replicated within the user’s application to communicate with multiple NVMe endpoints.
All data transfers occur through a user-defined, system-attached memory, such as an on-chip block RAM or off-chip DDR, connected to the PCIe Hard Block.
The IntelliProp NVMe Host Accelerator IP Core provides a small footprint processor register interface or RTL state-machine register interface for data movement between a user-defined data buffer and an NVMe target. Additionally, the NVMe Host Accelerator IP Core requires minimal knowledge of the PCIe and NVMe specification. The IP Core handles initialization of the PCIe Root Complex, building command submissions, parsing command
completions.
The protocol interface is compliant to the NVMe 1.4 specification and is fully verified using a coverage driven methodology in pseudo random simulation.
The IPC-NV164A-HI NVMe Host Accelerator IP Core provides a simple firmware or RTL driven interface for data movement to and from an NVMe endpoint attached to a PCIe link. The interface to the IP core is designed to be driven by a User Logic state machine or processor. All command submission and completion queues are managed by the internal state machines. Users will write command submission context to the Command Registers or direct wire connections and arm the Command Submission State Machine to issue a command to the NVMe endpoint. Users will read command completion context from the Command Registers or direct wire connections when command completions have been parsed by the Command Completion State Machine.
The NVMe Host Accelerator IP Core can be replicated within the user’s application to communicate with multiple NVMe endpoints.
All data transfers occur through a user-defined, system-attached memory, such as an on-chip block RAM or off-chip DDR, connected to the PCIe Hard Block.
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