On-chip AHB SRAM Memory Controller

CoreAhbSram provides an AHB bus interface to the embedded SRAM memory blocks within Microsemi's Flash devices. In these devices, software running on an AHB-based microprocessor will be able to read and write the embedded SRAM. CoreAhbSram implements a standard Slave AHB Bus 32-bit hardware interface. The core supports the ability to logically merge multiple SRAM blocks into one large area of SRAM.

• see the entire On-chip AHB SRAM Memory Controller datasheet
• get in contact with On-chip AHB SRAM Memory Controller Supplier