English
You are here:
ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash controller IP. MDLL sets the delay time for the control signal of PHY to access to the data in flash during the suitable period. Please refer to the following diagram for an overview of ONFI PHY
View ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC) full description to...
- see the entire ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC) datasheet
- get in contact with ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC) Supplier
Block Diagram of the ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
ONFI 4.1 PHY IP IP
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
- ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
- Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 - TSMC 5nm 5FF
- Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 - TSMC 6nm 6FF