Optimized for GHz+ operating speeds with minimum area and power consumption, ARC HS Processors are ideal for very high-performance embedded applications

The latest additions to the Synopsys ARC® ARC HS family, the 32-bit ARC HS5x and 64-bit HS6x processors, are based on the new ARCv3 instruction set architecture (ISA). The previous generation HS processors, based on the efficient ARCv2 instruction set architecture (ISA), include the HS3x, HS4x, and DSP-enhanced HS4xD processors. All HS processors support closely coupled memories (CCMs), which enable single-cycles access to instructions and data.

HS processors are optimized for GHz+ operating speeds with minimum area and power consumption, making them ideally suited for embedded applications with very high-performance requirements. The HS processors are available in single-core, dual-core and quad-core configurations.

The ARC HS processors are supported by a broad ecosystem of commercial and open-source tools, operating systems, and middleware. This includes offerings from leading industry vendors who are members of the ARC Access Program as well as a comprehensive suite of free and open source software available through the embARC.org website

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