Parameterizable RAM Built In Self Test

Features

• Fully static, synthesizable RAM BIST
• Independent Set of Test Algorithms for Application specific Test Coverage
• RAM Structure independent Algorithms
• Data Retention Rest
• Single Port (1RW) and Dual Port (1R1W, 2RW) Implementations
• Master Slave, simultaneous multiple RAM Test
• Optional transparent Bypass Mode (hidden RAM test during scan test)
• Optional Write Through Test Mode
• Optional Zero Output
• BIST Logic Scan testable
• JTAG controllable