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Parameterizable ROM Built In Self Test Controller
Features
- Fully static, synthesizable ROM BIST
- ROM Structure independent CRC Algorithms
- Master Slave, simultaneous multiple ROM Test
- Optional transparent Bypass Mode (hidden ROM test during scan test)
- Optional Zero Output
- BIST Logic Scan testable
- JTAG controllable
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ROM BIST IP
- Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 256 k
- STAR Memory System (SMS) Test & Repair IP
- STAR Memory System (SMS) Test & Repair IP for CAMs (Content Addressable Memories)
- STAR Memory System ECC IP
- Memory Compiler(12nm,16nm,22nm,28nm,40nm,55nm, 90nm, 115nm, 130nm, 150nm, 180nm)