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400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
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PCI Express GEN 4/5 Port SERDES PHY - Samsung 8LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY for PCIe 5.0 operates at 2.5Gbps, 5Gbps, 8Gbps, 16Gbps and 32Gbps, and is designed to meet higher performance standards required for enterprise market applications. The PHY additionally features an interface capability that allows integration with other customer-designed serial protocol PCS layers at any baud rate up to 16Gbps. The PMA is delivered as a hard macro while the fully-synthesizable soft PCS includes performing all necessary calibration and self-test functions. The universal PHY architecture allows forming arbitrarily wide efficient links by being independent of the need for a common CMU.
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SERDES IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Low-Latency SerDes PMA
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency