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PCI Express Gen 4 PHY
Features
- Support 16GT 8GT 5GT 2.5GT data rate
- Compliant with PCI Express 4.0, 3.1, 2.1, 1.1 and PIPE 4.2 standards
- x1, x2, x4, x8, x16 lane configuration with bifurcation
- Multi-tap adaptive programmable continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE)
- Support L1 SUB low power consumption mode status
- Support SRIS
- Built-in self-check vector, PRBS generation and check mechanism
- Temperature range -40℃-125℃
- Support Flip chip packaging
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PCIE PHY IP
- PCIe 6.0 PHY in TSMC (N6, N5, N4P, N3P, N3E)
- PCIe 6.0 PHY in Samsung (SF5A, SF4X, SF2)
- PCIe 7.0 PHY IP supporting the latest features of the evolving PCIe 7.0 specification to enable 128 GT/s and up to x16 lane configurations
- PCIe 7.0 PHY in TSMC (N5, N3P)
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, N7, N3P)