English
Aeonic Generate Digital PLL for multi-instance, core logic clocking
You are here:
PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 55nm SP process
PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process.
View PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 55nm SP process full description to...
- see the entire PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 55nm SP process datasheet
- get in contact with PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 55nm SP process Supplier
PCIe PHY IP
- PCIe 6.0 PHY in TSMC (N6, N5, N4P, N3P, N3E)
- PCIe 6.0 PHY in Samsung (SF5A, SF4X, SF2)
- PCIe 7.0 PHY IP supporting the latest features of the evolving PCIe 7.0 specification to enable 128 GT/s and up to x16 lane configurations
- PCIe 7.0 PHY in TSMC (N5, N3P)
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, N7, N3P)