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PCI Express (PCIe) 2.1 Controller
Application-optimized, high-performance controller IP for PCIe
The Cadence® Controller IP for PCIe® 2.0 is a solution created for less demanding designs. It has the logic required to integrate a Root Complex (RC), Endpoint (EP), or Dual Mode (DM) controller into any system on chip (SoC). Compliant with PCI Express® 2.1 and 1.1 specifications, the Controller IP has over then 100 configuration features, and 1500+ input parameters, to customize the controller to the specific needs of any application. The Controller IP is architected to quickly and easily integrate into any SoC, and connect seamlessly to a Cadence or third-party PIPE 4.2-compliant PHY. Client applications access the controller through an industry-standard Arm® AMBA® 4 or 3 AXI interface or through Cadence's native Host Adaptation Layer (HAL) interface.
The Cadence® Controller IP for PCIe® 2.0 is a solution created for less demanding designs. It has the logic required to integrate a Root Complex (RC), Endpoint (EP), or Dual Mode (DM) controller into any system on chip (SoC). Compliant with PCI Express® 2.1 and 1.1 specifications, the Controller IP has over then 100 configuration features, and 1500+ input parameters, to customize the controller to the specific needs of any application. The Controller IP is architected to quickly and easily integrate into any SoC, and connect seamlessly to a Cadence or third-party PIPE 4.2-compliant PHY. Client applications access the controller through an industry-standard Arm® AMBA® 4 or 3 AXI interface or through Cadence's native Host Adaptation Layer (HAL) interface.
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PCIe 2.1 IP
- PCIe Gen3 PHY
- PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface
- PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 3.1/2.1 PHY (6nm, 7nm, 12nm, 14nm, 16nm, 22nm, 28nm, 40nm and 55nm)