PCI Master/Target Interface Core

Features

• Flexible synthesizable HDL
• PCI specification 2.2 compliant
• 33 MHz performance
• 32-bit datapath
• Zero wait states burst mode
• Full bus Master/Target functionality
• Single interrupt support
• Type 0 Configuration space
• Support of all Base Address Registers
• Support of backend initiated target retry, disconnect and abort
• Parity generation and parity error detection.
• Available in synthesizable HDL source code
• DMA Controller Core supporting independent write and read operations available