PCI Master/Target with FIFO and AHB extensions

CorePCIF expands on the popular CorePCI by adding a FIFO interface. PCI is a complex interface with a wide variety of uses in computer and embedded systems applications. CorePCIF and CorePCI are the most versatile FPGA PCI cores available because each is capable of 33/66 MHz operation with either 32 or 64-bit bus widths in master, target, and master/target configurations. The master configuration includes a built-in DMA controller. CorePCIF-AHB is built on top of the CorePCIF core. It allows for both the AHB bus and PCI bus to initiate data transfers between the two buses. They work on all Microsemi's antifuse and flash product families, with latest inclusion being the SmartFusion2 devices.

Key Features of CorePCIF:
* Direct Master functions
* Built-in DMA controller
* Up to six configurable base address registers (BARs) plus expansion ROM support
* Supports up to six direct FIFO connections with no data loss
* Flexible backend data flow control
* Interrupt capability
* CardBus support
* Configurable user testbench
* Hot-swap extended capabilities support for compact PCI

Key Features of CorePCIF-AHB:
* Implements a PCI to AHB bridge
* Allows transfers to be initiated from the PCI or AHB side
* Supports asynchronous clocks
* Direct Master functions
* Built-in DMA controller
* Interrupt capability
* CardBus support
* Configurable user testbench
* Hot-swap extended capabilities support for compact PCI

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