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PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 55LL/SP/EF
PCIe Gen 2.0 PHY IP is a physical layer (PHY) IP solution for mobile, consumer and Enterprise applications that enable for a well equipped customization and complies with the PCIe2.0 standard specifications while incorporating mixed signal circuits to provide 2.5GT/s and 5.0GT/s data transfer speeds. Physical Media Attachment (PMA) and Physical Coding Sublayer (PCS) are the two levels that make up the PCIe2.0 PHY IP. It simply connects to either the PCIe2.0 MAC layer utilizing the industry-standard PIPE-3.0 interface.
The PCIe2.0 PHY IP transceiver is optimized for low power consumption and small die area while retaining great result and data throughput. The PCIe2.0 PHY IP includes an on-chip physical transceiver solution with ESD protection, a built-in self-test module with inbuilt jitter injection, and a dynamic normalization circuit that ensures full support for high-performance configurations.
The PCIe2.0 PHY IP transceiver is optimized for low power consumption and small die area while retaining great result and data throughput. The PCIe2.0 PHY IP includes an on-chip physical transceiver solution with ESD protection, a built-in self-test module with inbuilt jitter injection, and a dynamic normalization circuit that ensures full support for high-performance configurations.
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Block Diagram of the PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 55LL/SP/EF
