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PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
The PCIe2.0 PHY IP is a fully - featured physical layer (PHY) IP solution for mobile and consumer applications. The PHY IP integrates mixed signal circuits to enable both 2.5GT/s and 5.0GT/s data transfer speeds while conforming to the PCIe2.0 basic standards. The PCIe2.0 PHY IP is made up of two layers: the Physical Media Attachment (PMA) layer and the Physical Coding Sublayer (PCS), and it simply links to either the PCIe2.0 MAC layer through the use of the standard PIPE-3.0 interface.
The PCIe2.0 PHY IP transceiver is optimized for low power consumption and minimal die area, without sacrificing performance and high-data throughput. The PCIe2.0 PHY IP comprises a complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, built-in self-test module with embedded jitter injection, and a dynamic equalization circuit that ensures full support for highperformance designs.
The PCIe2.0 PHY IP transceiver is optimized for low power consumption and minimal die area, without sacrificing performance and high-data throughput. The PCIe2.0 PHY IP comprises a complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, built-in self-test module with embedded jitter injection, and a dynamic equalization circuit that ensures full support for highperformance designs.
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Block Diagram of the PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
