PCIe 3.0 PHY IP

We propound best in class fully customizable PCIe 3.0 PHY, targeted for both enterprise and client application, the complaint to PCIe 3.0 specification. The PHY IP is designed to carry a broad range of applications and can supply maximum throughput through its eight lanes configuration. The PHY supports PCIE3.0(8Gb/s/5Gb/s/2.5Gb/s) physical layer specifications.The PHY module comprises a top-level wrapper combining both the Physical Media Attachment (PMA) layer and the Physical Coding Sub-Block (PCS) layer.
The PHY provides a cost-effective solution that is designed to meet the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.

• see the entire PCIe 3.0 PHY IP datasheet
• get in contact with PCIe 3.0 PHY IP Supplier