PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC

To support high-bandwidth applications, PCIe 3.0 PHY IP provides a low-power, multi-lane, high-performance design. The PCIe 3.0 IP complies with the PIPE 4.3 standard and supports the whole spectrum of PCIe 3.0 Base applications. To enable PCIe 3.0 traffic at 8Gbps, the IP combines high-speed mixed signal circuits. Both the 2.5Gbps PCIe 1.0 data rate and the 5.0Gbps PCIe 2.0 data rate are backward compatible with it. The PCIe 3.0 IP may satisfy the needs for various channel circumstances since it supports both TX and RX equalisation approaches.

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