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PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
High-bandwidth applications can avail advantage of PCIe 3.0 PHY IP's high performance, multi-lane scalability, and low-power layout. A full variety of PCIe 3.0 Base applications are supported by the PCIe 3.0 IP, which also complies with the PIPE 4.3 specification. To enable PCIe 3.0 traffic at 8Gbps, the IP combines highspeed mixed signal circuits. Both the 2.5Gbps PCIe 1.0 data rate and the 5.0Gbps PCIe 2.0 data rate are backward compatible with it. The PCIe 3.0 IP may satisfy the needs for various channel circumstances since it supports both TX and RX equalization approaches.
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Block Diagram of the PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
PCIe 3.0 IP Cores IP
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 4.0 Controller with AMBA AXI interface
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP