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Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
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PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP
The PCIe 3.0 PHY IP is designed to support increased applications with its low-power, multi-lane, high-performance design. It fully supports a wide range of PCIe 3.0 Base applications and complies with the PIPE 4.3 specification. By integrating high-speed mixed signal circuits, the IP enables PCIe 3.0 traffic at 8Gbps. It maintains backward compatibility with transfer throughputs of 5.0 Gbps for PCIe 2.0 and 2.5 Gbps for PCIe 1.0. Additionally, it caters to various channel circumstances by supporting both TX and RX equalization approaches.
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Block Diagram of the PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP
PCIe3 IP
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- Multi-protocol SerDes PMA in FDSOI (GF22FDX FDX 22FDX) - PCIe1 PCIe2 PCIe3 PCIe4 and more
- Low Power PCIe3 SERDES PHY - TSMC 40G
- Low Power PCIe3/SATA3SERDES PHY - TSMC 28HPC+
- Low Power PCIe3/SATA3 SERDES PHY - TSMC 16FFC
- Low Power PCIe3/SATA3 SERDES PHY - TSMC 12FFC