PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 7nm

For the high-bandwidth applications, PCIe 3.0 PHY IP offers high-performance, multi-lane capabilities, and low-power design. The PCIe 3.0 IP complies with the PIPE 4.3 standard and supports the whole spectrum of PCIe 3.0 Base applications. High-speed mixed signal circuits are included into the IP to handle PCIe 3.0 traffic at 8Gbps. Both the 2.5Gbps PCIe 1.0 data rate and the 5.0Gbps PCIe 2.0 data rate are backward compatible with it. The needs for various channel conditions may be met by the PCIe 3.0 IP thanks to its support for both TX and RX equalization approaches.

• see the entire PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 7nm datasheet
• get in contact with PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 7nm Supplier