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PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 40LP
This PCIe 3.0 Base Specification-compliant Peripheral Component Interconnect Express Gen3 PHY supports the PIPE 4.3 interface standard. Due to the support of an extra PLL control, reference clock control, and inbuilt power gating control, low power consumption is accomplished. Additionally, because the low power mode option is customizable, the PHY is extensively useful for a variety of settings with diverse power consumption considerations. Utilizing a test bench created in Verilog HDL, NCVerilog simulation software is used to verify PCIe PHY operation.
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Block Diagram of the PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 40LP
pcie3.0ip IP
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