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PCIe 3.1 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
(PCIe 3.1) x4 PHY IP supports PCIe3.1 transmission. This is compliant with PCIe Rev3 Base Specification with support of PIPE 4.3 interface spec. Input clock frequency as 25Mhz, the output data rate(serial) supports all three 2.5 Gbps, 5.0 Gbps, 8.0 Gbps. 10 Pads is required, and the max clock speed is 500MHz. Operating Voltage Range: - 0.99V-1.21V, typical=1.1V - 2.97V-3.63V, typical=3.3V
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pcie 3.1 ip IP
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
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- PCIe 4.0 Controller with AMBA AXI interface
- Configurable controllers for PCIe 3.1 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications