PCIe Gen 3.1 transmission is supported by (PCIe 3.1) x4 PHY IP. With compatibility for PIPE 4.3 interface spec, this complies with PCIe Rev3 Base Specification. 2.5 Gbps, 5.0 Gbps, 8.0 Gbps, all three are supported by the output data rate (serial), which has a 25Mhz input clock frequency. 2.5, 5, and 8 gigabits per second. A minimum of 10 Pads and a maximum clock speed of 500MHz are needed. Range of operating voltages: - 2.97V-3.63V, typical =3.3V; 0.99V-1.21V, usual = 1.1V;