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PCIe 4.0 PHY on 8nm
The PCIe PHY IP consists of hardmacro PMA and softmacro PCS compliant to PCIe Base 4.0 specification. This IP offers a cost-effective and low-power solution using 8nm FinFet CMOS technology. It includes all ESD I/Os and bump pads, and supports extensive built-in self test features such as loopback and scan.
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Block Diagram of the PCIe 4.0 PHY on 8nm IP Core
PCIe 4.0 IP
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, N7, N3P)
- PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 4.0 Controller with AMBA AXI interface