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PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
For high-bandwidth applications, the PCIe 4.0 PHY IP delivers high-performance, multi-lane capabilities and a low-power design. A full variety of PCIe 4.0 Base applications are supported by the PCIe 4.0 IP, which also complies with the PIPE 4.4.1 specification. The IP integrates high-speed mixed signal circuits to support PCIe 4.0 traffic at 16Gbps. It is backward compatible with PCIe 3.1 data rate at 8.0Gbps, PCIe 2.1 data rate at 5.0Gbps and PCIe 1.1 data rate at 2.5Gbps. The PCIe 4.0 IP may satisfy the needs for various channel circumstances since it supports both TX and RX equalisation methods.
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Block Diagram of the PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
PCIe IP Core IP
- PCIe 5.0 Integrity and Data Encryption Security Module
- PCIe 6.1 Controller
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP