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PCIe 5.0 PHY
With sophisticated architecture and advanced technology, KNiulink SerDes PHY IP with PMA and PCS layer is designed for low power and high performance application. PCS layer and PMA layer include RX, TX and a common lane. The interfaces between users and IP are PIPE interface. All the control and configuration bits of the SerDes PHY IP are assigned in register map at PCS side and can be accessed through JTAG interface and register access port.
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PCIe 5.0，PHY IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N5, N4P, N3E, N3P)
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection