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PCIe 6.0 PHY on 4nm
The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 6.0 specification. This IP offers a cost-effective and low-power solution using 4nm FinFet CMOS technology. It includes all ESD I/Os and bump pads, and supports extensive built-in self test features such as loopback and scan.
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Block Diagram of the PCIe 6.0 PHY on 4nm IP Core
