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PCIe2.0 PHY & Controller
The Innosilicon SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datasheet, the PHY has been configured to support PCIe 2.0 specifically, but the PHY itself can be configured to support a wide range of HS SERDES protocols through changes to the PCS layer and register settings.
The PHY is physically configured in order to support multi-lane solutions. There is a common block with Tx PLL, reference clock input, bandgap, bias circuitry and termination calibration. This common block can then support up to 4 lanes of Tx/Rx.
The PHY is physically configured in order to support multi-lane solutions. There is a common block with Tx PLL, reference clock input, bandgap, bias circuitry and termination calibration. This common block can then support up to 4 lanes of Tx/Rx.
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PCIe2.0 IP
- PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface
- Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 28HPC process
- Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in GF 28SLP process
- Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 55LP process
- Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 65GP process
- 5G Multi-SerDes For PCIe2.0/USB3.0 PHY