Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 serial bus standard where SRIS (Separate RefClk Independent Spread-Spectrum clock generation) is required. This SSCG PLL is designed for digital logic processes and use robust design techniques to work in noisy SoC environments.
View
PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP+
full description to...
see the entire
PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP+
datasheet
get in contact with
PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP+
Supplier
No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.