English
You are here:
PCIe4/3/2/1 PHY & Controller
The Innosilicon PCIe4.0 PHY is a highly configurable PHY capable of supporting speeds up to 16Gbps within a single lane. For this particular datasheet, the PHY has been configured to support PCIe4.0 specifically, but the PHY itself can be configured to support a wide range of HS SERDES protocols through changes to the PCS layer and register settings.
The PHY is physically configured in order to support multi-lane solutions. There is a common block with Tx PLL, reference clock input, bandgap, bias circuitry and termination calibration. This common block can then support up to 4 lanes of Tx/Rx.
The PHY is physically configured in order to support multi-lane solutions. There is a common block with Tx PLL, reference clock input, bandgap, bias circuitry and termination calibration. This common block can then support up to 4 lanes of Tx/Rx.
View PCIe4/3/2/1 PHY & Controller full description to...
- see the entire PCIe4/3/2/1 PHY & Controller datasheet
- get in contact with PCIe4/3/2/1 PHY & Controller Supplier
PCIe4/3/2/1 PHY & Controller IP
- UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
- LPDDR3/2/DDR3/3L Combo PHY & Controller
- SDRAM DDR4/3/2 Host Controller & PHY
- SDRAM LPDDR5/4x/4/3/2 Host Controller & PHY
- SDRAM LPDDR5/4x/4/3/2 Host Controller & PHY - TSMC 16nm 16FFC,FF
- Compute Express Link (CXL) 2.0 Controller