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PCIe5.0 PHY & Controller
The Innosilicon Gen1/2/3/4/5 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, high reliability, low latency, low area, low power and easy to integrate PCI Express solution. This Controller supports Up to x8 Gen1 (2.5Gb/s), Gen2 (5.0Gb/s), Gen3 (8.0Gb/s), Gen4 (16Gb/s), Gen5 (32Gb/s), full compliant with PCI Express Base Specification, Revision 5.0.
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PCIe5.0 IP
- CCIX 1.1 Controller with AMBA AXI interface
- 32G Multi-SerDes For PCIe5.0/USB3.x PHY
- Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 28HPC process
- Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in GF 28SLP process
- Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 55LP process
- Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 65GP process