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PGA
The IP is a PGA based on SMIC 110nm process. It consists of 1 stages and a separate feedback offset cancellation DAC is used for de-offset removal.
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Block Diagram of the PGA IP Core
PGA IP
- 1~50V/V low offset PGA for SAR-ADC ; UMC 0.18um Mixed-Mode PROCESS
- 14-Bit 25MSPS Sigma-Delta ADC with PGA
- 14-Bit 25MSPS Sigma-Delta ADC with PGA
- Programmable gain amplifier PGA for Industrial process control and low power sensors
- PGA for 32b Analog Front End for Seismic Precision application in 180nm
- Programmable gain amplifier PGA for Industrial process control and low power sensors