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NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
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PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface
KA13UGPEP20ST001 provides a complete PHY layer solution for PCIe1.1/PCIe2.0 (2.5/5.0Gbps) for single lane application. It has a serial interface and PIPE3 compliant digital interface.
KA13UGPEP20ST001 offers a modular architecture, diagnostic access, and testability support, in addition to low power and small area.
KA13UGPEP20ST001 offers a modular architecture, diagnostic access, and testability support, in addition to low power and small area.
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