Search for Silicon IP

TSMC 22nm ULL Wirebond I/O Library with ultra-low leakage 1.8V GPIO, 1.8V I2C ODIO and 1.8V Analog Cell

• Typical leakage <1nA
• Worst case leakage <80nA
• 150MHz low-leakage GPIO

Highly customizable processor IP

• Highly customizable processor
• Supports the Lua scripting language.

USB 20Gbps Device Controller

• No need for external PHY for USB 3.2 Gen 1 and Gen 2 interface
• Uses in-built transceiver as PHY layer
• Requires less pins compared to external PHY

PCIe 5.0 PHY for TSMC N7

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization

MIPI SPMI Target Controller

• Compliance as per MIPI Alliance Specifiction version 2.0
• Support SCLK frequency Low Speed - 32kHz to 15MHz
• Support SCLK frequency High Speed - 32kHz to 26MHz

Low Power PLL for 55nm UMC ULP CMOS

• Wide range M, P, and N integer dividers.
• 40MHz – 550MHz output frequency range.
• Input frequency range 1.4MHz – 32MHz.

16G Serdes in SMIC 28HKCP

• SMIC 28HKCP

UCIE 2.0 Controller

• Compliant with UCIe 2.0 specification
• High bandwidth and low latency controller design

Doppler Channel IP Core

• Support for orbital heights (h) in the range from 200 to 2000 km
• Support for carrier frequencies ( fc) in the range from 137 to 2200 MHz

MIPI D-PHY Tx 4 Lanes on TSMC 7FF18 for Automotive

• Compliant with the MIPI D-PHY specification
• Fully verified hard macro
• Up to 2.5 Gb/s per lane

4K Video Scaler IP Core

• Technology independent soft IP Core for FPGA, SoC and ASIC devices
• Supplied as human readable VHDL source code (or Verilog on request)

Universal Chiplet Interconnect Express (UCIe) Controller

• Up to 32 GT/s Per Lane.
• Up to 512 Gbps Aggregate Bandwidth.
• Support PCIe 7.0/6.0 CXL Streaming mode.

Multi-protocol SerDes PMA

• Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
• Extremely low jitter suitable for Enterprise SerDes applications

On-chip Security Enclave - Digital IP delivered as RTL

• Fully digital IP delivered as RTL and hence can be used on all digital logic silicon nodes with the required foundry memories inc. OTP
• Support for external secure NVM

Embedded Hardware Security Module (EVITA-Full Compliant)

• Pre-integrated CPU
• Full suite of hardware-accelerate cryptographic engine (Meet EVITA-Full requirements)

PCIe 5.0 PHY for TSMC N3P

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
• Lane margining at the receiver

UCIe-S PHY, Standard Package

• Compliant to UCIe 2.0 specifications
• Supports MCM, BGA and Chiplet2Chiplet interconnects on PCB
• Speed up to 32GT/s per lane (insertion loss and process dependent)

1.6T Ultra Ethernet IP Solution with PHY, Controller and Verification IP

• Ethernet MAC, PCS and PHY to complete a full Ultra Ethernet interface stack
• Supports evolving IEEE 802.3 and OIF-224G electrical standards

UALink IP Solution with PHY, Controller and Verification IP

• Lightweight, low latency IP solution for XPU to XPU interconnects optimized for AI workloads
• Complete UALink IP solution with Controller, PHY and VIP, fully integrated for AI accelerators (XPUs), GPUs, and switches

5-60V Input Buck Regulator (Type-C EPR compatible)

• Wide operating voltage range 4.5V – 60V.
• Output voltage optionally 5V, or 3.3V.
• Soft start.

Universal Chiplet Interconnect Express (UCIe) Controller

• Up to 32 GT/s Per Lane.
• Up to 512 Gbps Aggregate Bandwidth.
• Support PCIe 7.0/6.0 CXL Streaming mode.

12-bit SAR ADC TSMC

FlexNoC 5 Network-on-Chip (NoC)

• Physical Awareness for faster timing closure
• Higher margins
• Fewer wires

28G Ethernet PHY IP for TSMC N7

• Supports 1.25 to 32 Gbps data-rate
• Supports PCI Express 5.0, 1G to 400G Ethernet, CCIX, CXL, and SATA protocols