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55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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PLL 3.2GHz
This IP is a phase locked loop which base on TSMC 40nm. It integrates a Phase Frequency detector (PFD), a Charge Pump (CP), a Low Pass Filter (LPF), a Voltage Control Oscillator (VCO) and other associated blocks. All fundamental building blocks as well as fully programmable dividers are integrated on the core. It is developed as a macro cell for clock generator and frequency synthesizer. The output frequency can be up to 3.2GHz. This IP supports operation voltage is 1.1V.
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Block Diagram of the PLL 3.2GHz IP Core
