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PLL (Frequency Synthesizer) IP, Input: 133MHz - 266MHz, Output: Output: 133MHz - 266MHz, 266MHz - 533MHz, 533MHz - 1066MHz, UMC 0.13um HS/FSG process
Input 133MHz - 266MHz, output clock_1X 133MHz - 266MHz, output clock_2X 266MHz - 533MHz, output clock_4X 533MHz-1066MHz, frequency synthesizable PLL, UMC 0.13um HS/FSG Logic process.
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