English
You are here:
PLL IP, Input: 25MHz/50MHz/100MHz/125MHz, Output: 25MHz/125MHz/1.25GHz, UMC 0.13um HS/FSG process
high speed clock generator using UMC 0.13um 1.2V HS process.
View PLL IP, Input: 25MHz/50MHz/100MHz/125MHz, Output: 25MHz/125MHz/1.25GHz, UMC 0.13um HS/FSG process full description to...
- see the entire PLL IP, Input: 25MHz/50MHz/100MHz/125MHz, Output: 25MHz/125MHz/1.25GHz, UMC 0.13um HS/FSG process datasheet
- get in contact with PLL IP, Input: 25MHz/50MHz/100MHz/125MHz, Output: 25MHz/125MHz/1.25GHz, UMC 0.13um HS/FSG process Supplier
PLL/DLL IP
- Programmable DLL, fully digital PLL - TSMC 28nm 28HP (CLN28HP)
- Programmable DLL, fully digital PLL - TSMC 40nm 40G (CLN40G)
- Programmable DLL, fully digital PLL - TSMC 40nm 40LP (CLN40lp)
- Fully Digital Glitch Free PLL TSMC HPC+28nm - 200-2000 MHz
- High Performance Fractional-N RF Frequency Synthesizer PLL in UMC 40LP
- Fractional-N PLL for Performance Computing in GlobalFoundries 22FDX