Power & area optimized: 2–3-stage, single-issue pipeline, as small as 13.5k gates

The E2 Series is highly optimized for area and power while still offering class-leading performance. Targeted for microcontroller and embedded devices, the E2 Core can be configured to be as small as 13.5k gates with an efficient 2-stage pipeline or configured for higher performance with a 3-stage pipeline, hardware floating-point, instruction cache, and more.

With SiFive Core Designer, the E2 Series can be fully customized to meet your specific requirements.

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