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PowerPC Bus Slave
Features
- Fully supports PowerPC 60x bus protocol including PowerPC 603, 604, 740, 750 and MPC8260.
- Designed for ASIC or PLD implementations in various system environ-ments.
- Fully static design with edge triggered flip-flops.
- Direct support for standard asynchronous SRAM and synchronous BURST SRAM.
- Burst access support using conventional asynchronous SRAM.
- Additional back-end interface bus for on-chip and off-chip logic and register access.
- Back-end interface supports user device with various wait states.
- Burst access support including MPC8260 extended transfer size.
- Write buffer supports write posting for the back-end bus interface.
- Handles separate address bus and data bus tenure.
- Supports PowerPC address pipeline for improve performance.
- Supports address bus retry generated by other external device.
- Qualified address data bus grant through the use of bus busy signals.
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PowerPC Bus Slave IP
- I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
- I2C Master / Slave Controller w/FIFO (APB Bus)
- I2C Slave Controller w/FIFO (APB or AHB or AHB-Lite or AXI-Lite Bus)
- I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
- I2C Slave Controller w/FIFO (AXI Bus)
- I2C Slave Controller w/FIFO (AHB Bus)