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1.8V/3.3V I2C 5V Failsafe Failtolerant Automotive Grade 1 in GF (12nm)
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Processor Memory Aliasing
CoreRemap is an APB slave that is a small control block with a singlebit register that is intended for use in control aliasing of memory resources at the bottom of the processor address space. Typically the nonvolatile Flash is located at slot 0 at the bottom of the memory map by default, but the SRAM may be made to appear at the base of the address space by setting Remap high (in which case slot 0 is addressable as slot 1). The Remap Default input determines the value of the Remap output following a reset.
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