English
You are here:
Programmable CMOS frequency divider (32...16383 dividing ratio)
The programmable CMOS frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3. This structure is especially effective for wide range of dividing ratio since the number of triggers to accomplish the specified ratio is minimized. The dividing ratio is 32...16383.
Input frequency is 100...1050 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
Input frequency is 100...1050 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
View Programmable CMOS frequency divider (32...16383 dividing ratio) full description to...
- see the entire Programmable CMOS frequency divider (32...16383 dividing ratio) datasheet
- get in contact with Programmable CMOS frequency divider (32...16383 dividing ratio) Supplier
Programmable CMOS frequency divider N-divider IP
- Programmable 9-bit CMOS frequency divider (2…511 dividing ratio)
- Programmable CMOS frequency divider (56..16383 dividing ratio)
- Programmable CMOS HF divider (16…4095 dividing ratio)
- Programmable frequency divider (56 to 16383 dividing ratio)
- Phase-locked loop clock generator
- Wide band 3Ghz-6GHz integer phase-locked loop