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55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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Programmable CMOS PLL high-frequency divider
The CMOS PLL high-frequency divider consists of the converter of a differential input signal to an unipolar signal with a supply voltage peak-to-peak, a prescaler with variable dividing ratio 8/9 and two binary decade counters.
The block is fabricated on TCMS BiCMOS 0.18 um technology.
The block is fabricated on TCMS BiCMOS 0.18 um technology.
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